TY  - BOOK
AU  - Minns, Peter
AU  - Elliot, Ian D.
TI  - FSM-based digital design using Verilog HDL
SN  - 9780470060704
AV  - TK 7888.3 .M56 2008 
PY  - 2008///
CY  - England
PB  - John Wiley & Son, Inc.
KW  - VERILOG (COMPUTER HARDWARE DESCRIPTION LANGUAGE)
N1  - Includes index; Introduction to Finite-State Machines and State Diagrams for the Design of Electronic Circuits and Systems -- Using State Diagrams to Control External Hardware Subsystems -- Synthesizing Hardware from a State Diagram -- Synchronous Finite-State Machine Designs -- One Hot Technique in Finite-State Machine Design -- Introduction to Verilog HDL -- Elements of Verilog HDL -- Describing Combinational and Sequential Logic using Verilog HDL -- Asynchronous Finite-State Machines -- Introduction to Petri Nets
N2  - As digital circuit elements decrease in physical size, resulting in increasingly complex systems, a basic logic model that can be used in the control and design of a range of semiconductor devices is vital. Finite State Machines (FSM) have numerous advantages; they can be applied to many areas (including motor control, and signal and serial data identification to name a few) and they use less logic than their alternatives, leading to the development of faster digital hardware systems. This clear and logical book presents a range of novel techniques for the rapid and reliable design of digit
ER  -