000			02100nam a2200241Ia 4500
003			NULRC
005			20250520100610.0
008			250520s9999 xx 000 0 und d
020			_a9780521769921
040			_cNULRC
050			_aQA 76.5 .B34 2010
100			_aBaer, Jean-Loup. _eauthor
245		0	_aMicroprocessor architecture : _bfrom simple pipilines to chip multiprocessors / _cJean-Loup Baer
260			_aCambridge : _bCambridge University Press, _cc2010
300			_axiv, 367 pages : _billustrations ; _c26 cm.
365			_bUSD57.73
504			_aIncludes bibliographical references and index.
505			_aIntroduction -- The basics -- Superscalar processors -- Front-end : branch predictio, instruction fetching, and register renaming -- Back-end : instruction scheduling, memory access instructions, and clusters -- The cache hierarchy -- Multiprocessors -- Multithreading and (chip) multiprocessing -- Current limitations and future challenges.
520			_aThis book gives a comprehensive description of the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars. It discusses topics such as: • The policies and mechanisms needed for out-of-order processing such as register renaming, reservation stations, and reorder buffers • Optimizations for high performance such as branch predictors, instruction scheduling, and load-store speculations • Design choices and enhancements to tolerate latency in the cache hierarchy of single and multiple processors • State-of-the-art multithreading and multiprocessing emphasizing single chip implementations Topics are presented as conceptual ideas, with metrics to assess the performance impact, if appropriate, and examples of realization. The emphasis is on how things work at a black box and algorithmic level. The author also provides sufficient detail at the register transfer level so that readers can appreciate how design features enhance performance as well as complexity.
650			_aMICROPROCESSORS
700			_aBaer, Jean-Loup. _eco-author
942			_2lcc _cBK
999			_c9066 _d9066